A blog series by Zoltán Gyenge and Thomas Wyder
(Software Practice Group at Rentsch Partner)
In Part I of this blog series, we explored how the Enlarged Board of Appeal’s landmark decision G 1/23 refined the “disclosure test” under the EPC, recognizing de facto disclosure, associated with factual availability, as prior art while maintaining the higher standard of enabling disclosure for patentability.
In Part II, we examined how a “grey box” phenomenon arises in relation to different levels of transparency associated with embedded firmware. Typically, the internal logic of a product running with embedded firmware remains hidden, while its observable behavior is sufficient to constitute prior art under the European Patent Convention (EPC). In Part III, we move to the domain of advanced semiconductor devices, where the same legal principle meets one of the most technologically demanding industries.
The Scenario: 1-Nanometer Chips on the Market
At the time of writing (August 2025), the most advanced chips available on the market rely on 3-nanometer process technology. Research at even smaller scales is being performed worldwide, but no one is currently able to produce functional chips at the 1-nanometer scale.
Let us assume that an innovative company makes a breakthrough and succeeds in fabricating a 1-nanometer semiconductor chip using a proprietary process. Said company places the chip on the market. Subsequently, competitor files a patent application, which receives an effective date. At this date, the physical structure of the chip can be fully analyzed using the best microscopy and spectroscopy techniques available, which would allow the skilled person to understand its layout and internal architecture in detail. However, no known fabrication technology exists at this time which would allow the skilled person to reproduce such a chip.
This scenario mirrors the firmware example from Part II but now in the context of cutting-edge hardware: the chip is publicly available and analyzable, yet this piece of hardware for far remains irreproducible.
The Disclosure Double Standard of G 1/23
The sketched semiconductor scenario allows bringing the double standard emerging from G 1/23 into focus.
- No Requirement of Reproducibility for a Product to Constitute Prior Art
Following the Enlarged Board of Appeal’s decision in G 1/23, the public availability of the chip is sufficient for it to constitute prior art. Whether the skilled person can reproduce the product is irrelevant for the question as to whether it constitutes prior art. The market release of the 1nanometer chip therefore blocks competitors from patenting of the same chip structure, even though the public has not received any information that would allow reproduction. - Enablement Requirement for Patentability
The asymmetry becomes evident when considering that if one were to file a patent application for the chip, even if the claims were directed only to the chip structure, the application would need to meet the enablement requirement of Article 83 EPC. The skilled person must be able to put the invention into practice without undue burden. This effectively means that the manufacturing method must be disclosed to obtain a patent.
This leads to a stark contrast: Simply placing the chip on the market suffices to prevent competitors from patenting the chip structure, but obtaining a patent would require laying open a fullly enabling disclosure. Thus, deciding not to patent a chip and to instead just put it on the market effectively constitutes a decision: ´If I do not patent it, no one can´.
Implications for Practitioners: Patent your Chip and/or Keep it Secret?
For semiconductor innovators, the practical consequences are significant. Now, more than ever before, an informed decision needs to be taken in advance, prior to putting a new chip on the market, by balancing several strategic tools:
- which aspects to cover by a patent application;
- which aspects of the chip to keep secret; and
- which information to publicly disclose about the chip, to fine-tune your de facto disclosure to establish hurdles limiting competitors in their own patenting endeavors.
Filing a patent application secures enforceable rights but forces the applicant to reveal the manufacturing method, which competitors could study and build upon.
Maintaining trade secrets preserves confidentiality but offers no active rights against copycats, should they eventually develop the capability to reproduce the chip independently.
Putting a new chip on the market, thereby creating de facto disclosure, and, if desirable, purposefully enhancing said de facto disclosure by adding selective pieces of information, can be used to strategically craft the balance between the difficulties competitors face in developing themselves vs. claiming any new invention.
In summary, a hybrid IP strategy for chips may be advisable. Companies could file selected patent applications on reproducible sub‑processes or chip elements which mature into enforceable patents, while maintaining trade secrets for the most critical fabrication steps that cannot be reverse engineered.
Planning the strategy must take place well before the first commercial release of a next‑generation chip. The sketched hybrid approach would safeguard against a competitor later patenting the chip, thereby proactively reducing the risk of future infringement claims against the chip itself.
Moreover, if a competitor were to independently develop and patent a manufacturing process for the same chip at a later date, the company who had previously put the chip on the market can rely on the so‑called right of continued use of its existing process. This would allow continued practice of the process without infringing a patent based on a later filing, though such a strategy must be approached cautiously, as the right of continued use is to be construed narrowly and the precise terms are fact‑dependent in view of the respectively applicable national law.
Shifting the Balance in the Contract Theory of Patents
The contract theory of patents holds that the state grants a time‑limited monopoly in exchange for a technical teaching that enriches the public domain. This quid pro quo works well in two clear-cut cases:
- Black boxes, which are entirely opaque. They do not constitute any meaningful prior art and do not prevent others from filing patents with an enabling disclosure.
- Transparent boxes, which are fully analyzable and reproducible. They form part of the state of the art and prevent future patents, but in return the public gains an enabling teaching that fuels cumulative innovation.
The 1-nanometer chip scenario belongs to a third category (introduced already and discussed in Parts I and II of this blog series): the grey box. The chip is publicly available and analyzable, so it prevents later patents. Yet it remains irreproducible, offering no enabling disclosure to society.
By releasing a grey box product, a company can undermine the incentive to disclose without providing the public with a corresponding technical benefit. The risk is that step‑by‑step market releases could eat away at the public interest. They may preclude future patenting opportunities without fulfilling the quid pro quo that the patent system is designed to maintain.
Conclusion
For companies working at the forefront of chip technology, what was put down by the Board of Appeal in the landmark decision G 1/23 is more than a theoretical nuance. It challenges long‑standing intellectual property strategies that traditionally relied on a predictable balance between patenting and trade secrets. The old playbook of patenting groundbreaking developments as broadly as possible may no longer be sufficient or optimal. Relying on a more subtle interplay between patents and trade secrets, i.e., which elements to disclose and which to keep confidential, and optimizing the strategy before market release of a new chip now appears favorable.
